1. Field of the Invention
The present invention relates to a DRAM structure (Dynamic Random Access Memory) with a transistor formed in a floating body or well and a method of reading, writing and holding information in such a DRAM structure.
2. Discussion of the Related Art
FIG. 1 schematically shows a conventional example of a DRAM 5 comprising memory cells distributed in rows and in columns. Only four memory cells T1,1, T1,2, T2,1, T2,2 distributed in two rows and two columns are shown. Each memory cell corresponds to a MOS-type field effect transistor. The drains of the memory cells of a same column are connected to a drain line DLi, i being equal to 1 or 2 in the present example, also called bit lines. The gates of memory cells of a same row are connected to a gate line GLi, i being equal to 1 or 2 in the present example, also called a word line. The sources of the memory cells of a same row are connected to a source line SLi, with i ranging between 1 and 2 in the present example.
FIG. 2 is a simplified cross-section view of an example of a memory cell of DRAM 5, for example, memory cell T1,1. Memory cell T1,1 comprises an N-channel MOS transistor 10 formed in a floating body region 11 laterally delimited by an insulating ring 12 and, depthwise, by an N-type layer 13 formed in a P-type substrate 14. MOS transistor 10 comprises, on either side of gate region 16 surrounded with spacers 17 and resting on a gate insulator 18, N-type source and drain regions 19 and 20. Each of the source and drain regions comprises a deeper, more heavily doped region outside of the region defined by spacers 17 and a shallower, less heavily-doped region under the spacers. Drain line DL1 is connected to drain region 20, source line SL1 is connected to source region 19, and gate line GL1 is connected to gate 16.
In the absence of a specific action on the memory cell, floating body 11 is at a given potential corresponding to the thermal balance. It has been shown that positive or negative charges could be injected into this body, setting the selected memory cell(s) to one or the other of two determined states which will be called 1 and 0. According to this substrate biasing, the threshold voltage of the transistor modifies and states 1 and 0 can thus be distinguished.
Further, FIG. 2 shows an N-type conductive well 21 connecting with buried layer 13 to enable biasing hereof. In FIG. 2, the biasing terminal is called NISO, and buried layer 13 can be called the insulation layer. Biasing terminal NISO is maintained at a constant value, preferably at a slightly positive value.
In the following description, the given example corresponds to a technology in which the minimum possible dimension of a pattern is on the order of 0.12 μm and in which a gate length on the order of 0.30 μm and a depth of insulating regions 12 on the order of 0.35 μm have been selected, as well as a gate oxide thickness on the order of 6 nm.
FIG. 3 shows the voltages to which the control lines of memory 5 of FIG. 1 are brought in the case of a hold operation, also called operation of retention of the data stored in the transistors. Such an operation is the operation by default of memory 5, that is, in the absence of a data read or write operation in the memory cells. Conventionally, all the control lines are set to the reference voltage of memory 5, generally ground potential, defined as equal to 0 V in the exemplary descriptions hereafter. Thereby, all transistors are blocked and the data stored in the transistors is not modified.
FIG. 4 shows the voltages to which the control lines of memory 5 of FIG. 1 are brought for an operation of writing a “1” into memory cell T1,1. As compared with the hold operation, drain line DL1 is set to a high voltage, for example, +2.5 V. It may be the voltage provided by the positive power supply source (Here please insert a reference numeral corresponding to a block representing a power supply source to be added to the drawing) of memory 5. Gate line GL1 is set to a voltage intermediary between the reference voltage and the high voltage, in the present example, 1.2 V. Transistor T1,1 is then on, the other memory transistors being off. The drain-source voltage of transistor T1,1 being high, transistor T1,1 is set to a relatively strong conduction state. At the end of this state, when all the voltages of the control lines are brought back to zero, positive charges (holes) have accumulated in the floating body. Once memory cell T1,1 is at equilibrium, these charges tend to narrow the space charge areas at the level of the junctions delimiting body 11. Transistor T1,1 then has a low threshold voltage, that is, in a read state in which the transistor is slightly biased to the on state, a first current will be observed for a given gate voltage.
FIG. 5 shows the voltages to which the control lines of memory 5 of FIG. 1 are brought in an operation of writing of a “0” into memory cells T1,1 and T1,2 of memory 5. Such an operation is also called an erasing operation. As compared with the hold operation, gate line GL1 and source line SL1 are set to a low voltage, for example, −1.2 V. Each of transistors T1,1 and T1,2 is off, its gate and its source being set to a negative voltage, whereby the positive voltages possibly present in body 11 are eliminated and negative charges are injected after the setting to the on state of the body-source diode. At the end of this state, the space charge areas of the junctions delimiting body 11 tend to widen and this results in an increase in the transistor threshold voltage. Transistors T1,1 and T1,2 then have a high threshold voltage.
FIG. 6 shows the voltages to which the control lines of memory 5 of FIG. 1 are brought in the case an operation of reading the data stored in memory cell T1,1. As compared with the hold operation, drain line DL1 and gate line GL1 are set to 1.2 V. Transistor T1,1 is thus slightly biased to the on state. The threshold voltage of transistor T1,1 depends on the data memorized in transistor T1,1. Thus, in read conditions in which the transistor is slightly biased to the on state, a lower current is obtained for a same 1.2-V gate voltage when datum “0” is stored in transistor T1,1 and a higher current is obtained when datum “1” is stored in transistor T1,1. By “datum” is meant information in the form of a binary data bit, e.g. bit “0” or bit“1”. The current flowing through the MOS transistor is measured or, preferably, compared with a reference value ranging between the current values corresponding to states 1 and 0. Thus, the memory effect of a memory cell according to an embodiment of the present invention characterizes by a difference between a current at state 1 and a current at state 0 for a given drain-source biasing and for a given gate voltage.
A disadvantage of such a memory 5 is that an operation of writing of a datum “1” into a memory cell can modify the data stored in the memory cells of the same column. Indeed, as shown in FIG. 4, in an operation of writing into memory cell T1,1, the drain and the source of memory cell T2,1 are set to voltages, respectively of 2.5 V and 0 V.
In this case, the capacitive coupling exerted by the drain on body 11 of memory cell T2,1 causes an increase in the voltage of body 11 of memory cell T2,1. This voltage increase tends to forward bias the source junction of memory cell T2,1. The positive charges possibly stored in body 11 can thus leak through the source junction, causing a decrease in the number of positive charges stored in body 11. It may then no longer be possible to detect that datum “1” is stored in such a memory cell.